DocumentCode
1607580
Title
A 5 volt 0.5 μm mixed BiCMOS/CMOS channelless gate array
Author
Wong, Thomas
Author_Institution
Hitachi America Ltd., Brisbane, CA, USA
fYear
1992
Firstpage
435
Lastpage
438
Abstract
A 0.5-μm BiCMOS/CMOS gate array that incorporates a new basic cell topology with an uneven mix of MOS and bipolar devices is described. This approach is aimed at maximizing the utilization of a BiCMOS gate array by enabling three kinds of macros to be implemented without any silicon penalty: low-power CMOS, high-drive CMOS, and BiCMOS. Fabricated with 0.5-μm BiCMOS technology, the 5-V gate array features input and output buffers that can support TTL and ECL logic levels, as well as pseudo-ECL levels
Keywords
BiCMOS integrated circuits; CMOS integrated circuits; application specific integrated circuits; cellular arrays; logic arrays; logic design; 0.5 micron; 5 V; ECL logic levels; TTL logic levels; cell topology; channelless gate array; high-drive CMOS; low-power CMOS; mixed BiCMOS/CMOS; pseudo-ECL levels; BiCMOS integrated circuits; CMOS logic circuits; Clocks; Integrated circuit interconnections; Logic arrays; MOS devices; Macrocell networks; Qualifications; Routing; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270253
Filename
270253
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