Title :
High Performance and High Efficiency Memory Management System for H.264/AVC Application in the Dual-Core Platform
Author :
Zhang, Nai-Ran ; Li, Mo ; Li, Yang-Yang ; Wu, Wu-Chen
Author_Institution :
VLSI & Syst. Lab., Beijing Univ. of Technol.
Abstract :
This paper proposes memory management system for multimedia application based on dual-core platform. To use memory bus bandwidth efficiently and reduce memory bus transition, two steps store optimization in control level is adopted and bus efficiency increases nearly 35% compared with former scheme. To harmonize different master requirement, reasonable schedule level arranges memory access priority. Under these two levels, memory controller can cope with H.264 HDTV decoder 1920times1080 @ 30 frames per sec real time access clocking at 100 MHz. Moreover, this VLSI design is convenient to be integrated into different multimedia processing platform
Keywords :
DRAM chips; VLSI; high definition television; memory architecture; multimedia computing; optimisation; storage management; storage management chips; video codecs; video coding; DRAM technology; H.264/AVC application; VLSI design; dual-core platform; memory access priority; memory bus transition; memory controller; memory management system; multimedia application; Automatic voltage control; Bandwidth; Conference management; Control systems; DRAM chips; Decoding; HDTV; Memory management; Random access memory; Technology management; DDR SDRAM; Dual-Core; H.264/AVC; Memory management;
Conference_Titel :
SICE-ICASE, 2006. International Joint Conference
Conference_Location :
Busan
Print_ISBN :
89-950038-4-7
Electronic_ISBN :
89-950038-5-5
DOI :
10.1109/SICE.2006.314641
