• DocumentCode
    1607813
  • Title

    45nm node planar-SOI technology with 0.296 μm2 6T-SRAM cell

  • Author

    Yang, Fu-Liang ; Huang, Cheng-Chuan ; Huang, Chien-Chao ; Chung, Tang-Xuan ; Chen, Hou-Yu ; Chang, Chang-Yun ; Chen, Hung-Wei ; Lee, Di-Hong ; Liu, Sheng-Da ; Chen, Kuang-Hsin ; Wen, Cheng-Kuo ; Cheng, Shui-Ming ; Yang, Chang-Ta ; Kung, Li-Wei ; Lee, Chiu

  • Author_Institution
    Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
  • fYear
    2004
  • Firstpage
    8
  • Lastpage
    9
  • Abstract
    The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 μm2. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 μA/μm for N-FET and P-FET, respectively. The P-FET current is the best reported so far.
  • Keywords
    MOSFET; SRAM chips; semiconductor device noise; silicon-on-insulator; 0.296 μm2 6T-SRAM cell; 0.6 V; 120 mV; 130 nm; 140 nm; 45 nm; 45nm node planar-SOI technology; N-FET; P-FET; Capacitive sensors; Isolation technology; Lifting equipment; Lithography; Optical noise; Random access memory; Silicides; Silicon; Space technology; Sun;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8289-7
  • Type

    conf

  • DOI
    10.1109/VLSIT.2004.1345362
  • Filename
    1345362
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1607813