DocumentCode
1607883
Title
Scan cell design for enhanced delay fault testability
Author
Van Brakel, Gerrit ; Xing, Yizi ; Kerkhoff, Hans G.
Author_Institution
MESA Res. Inst., Twente Univ., Enschede, Netherlands
fYear
1992
Firstpage
372
Lastpage
375
Abstract
Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell
Keywords
delays; design for testability; fault location; logic design; logic testing; sequential circuits; DFT; circuit controllability; delay fault testability; gate array; layout; observability; scan cell design; scannable sequential circuits; Circuit faults; Circuit testing; Clocks; Delay; Hazards; Latches; Robustness; Sequential analysis; Sequential circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270266
Filename
270266
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