Title :
An algorithm for the optimization of channel definition using global routing information
Author :
Bobba, Vijay S. ; Russell, Warren T.
Author_Institution :
Nat. Semicond., Santa Clara, CA, USA
Abstract :
An algorithm is developed to optimize the channel models used by many of the existing channel routers for block layout. Optimization is performed by considering the global routing information at the channel intersection points. An explanation is given of the motivational aspects behind the development of the proposed method and its use in resolving the bottleneck issues that are encountered during the channel definition phase
Keywords :
VLSI; circuit layout CAD; optimisation; VLSI layout; algorithm; block layout; bottleneck issues; channel intersection points; channel models; global routing information; optimization of channel definition; Compaction; Design automation; Design methodology; Design optimization; Geometry; Integrated circuit interconnections; Programmable logic arrays; Read only memory; Routing;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100281
