Title :
A 78nm 6F2 DRAM technology for multigigabit densities
Author :
Fishburn, F. ; Busch, B. ; Dale, J. ; Hwang, D. ; Lane, R. ; McDaniel, T. ; Southwick, S. ; Turi, R. ; Wang, H. ; Tran, L.
Author_Institution :
Process R&D Center, Micron Technol. Inc., Boise, ID, USA
Abstract :
This paper discusses a manufacturable 6F2 DRAM technology at a 78nm half-pitch feature size that results in the smallest DRAM cell size (0.036 μm2) to date. The novel 6F2 cell design utilizes line/space patterning and self-aligned etches to improve process margin. An MINI capacitor that employs composite high-k dielectric materials is integrated into the process. Tungsten-clad WL and BL reduce parasitics and noise to make this 6F2 technology suitable for 2Gb-4Gb density DRAM with a competitive die size for volume production.
Keywords :
DRAM chips; VLSI; etching; nanolithography; 2 to 4 Gbit; 78 nm; 78nm 6F2 DRAM technology; MINI capacitor; composite high-k dielectric materials; line/space patterning; multigigabit densities; process margin; self-aligned etches; Capacitors; Composite materials; Etching; High K dielectric materials; High-K gate dielectrics; Noise reduction; Production; Pulp manufacturing; Random access memory; Space technology;
Conference_Titel :
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8289-7
DOI :
10.1109/VLSIT.2004.1345374
