High performance DSP ASIC for multiply, divide and square root

Author

Woods, R.F. ; McQuillan, S.E. ; Dowling, J. ; McCanny, J.V.

Author_Institution

Dept. of Electr. & Electron. Eng., Queen´´s Univ. of Belfast, UK

fYear

1992

Firstpage

209

Lastpage

213

Abstract

The design of a high-speed ASIC that combines the operations of multiplication, division and square root is described. The chip is based on a systolic array architecture that uses a redundant number system and allows multiplication, division, and square root to be combined on the same hardware. The chip has been designed using a 1.5-μm, double-metal CMOS technology, operates on 16-b sign magnitude data, and has a throughput rate of 40 Msample/s for each operation

Keywords

CMOS integrated circuits; application specific integrated circuits; digital arithmetic; digital signal processing chips; systolic arrays; 1.5 micron; 16-b sign magnitude data; DSP ASIC; division; double-metal CMOS technology; multiplication; redundant number system; square root; systolic array architecture; throughput rate; Algorithm design and analysis; Application specific integrated circuits; Arithmetic; CMOS technology; Digital signal processing; Hardware; Signal processing algorithms; Systolic arrays; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270275

Filename

270275