Title :
Fully working 1.10 μm2 embedded 6T-SRAM technology with high-k gate dielectric device for ultra low power applications
Author :
Ryu, Hyuk-Ju ; Chung, Woo-Young ; Jang, You-Jean ; Lee, Yong-Jun ; Jung, Hyung-Seok ; Oh, Chang-Bong ; Kang, Hee-Sung ; Kim, Young-Wug
Author_Institution :
Syst. LSI Div., Samsung Electron. Co. Ltd, Kyonggi-do, South Korea
Abstract :
Ultra low power 1.10 μm2 6T-SRAM chip with HfO2-Al2O3 gate dielectric was for the first time successfully demonstrated for the system-on-chip applications. By carefully optimizing gate pre-doping process, gate leakage current was dramatically suppressed and poly deletion was reduced. Device performance was improved by 15% and 12% for NFET and PFET, respectively. The threshold voltage of long channel transistor was well controlled to the acceptable value (0.4V) by channel engineering. Equivalent oxide thickness of HfO2-Al2O3 film was 17Å and gate leakage current density was 1600-times lower than that of the oxynitride. Current performance of 90nm gate length NFET and PFET with HfO2-Al2O3 were 335 and 115 μA/ μm, while Ioff were 0.9 and 2.0pA/ μm, respectively. SNM value of 1.10 μm2 6T-SRAM bit cell was 340mV at Vdd = 1.2V. Stand-by current of the SRAM chips with HfO2-Al2O3 was decreased by 2 orders, while access time was 1.65 times larger compared with that of SRAM chips with oxynitride at Vdd = 1.2V.
Keywords :
MOSFET; SRAM chips; VLSI; leakage currents; nanolithography; permittivity; HfO2-Al2O3; NFET; PFET; embedded 6T-SRAM technology; gate leakage current; gate pre-doping process; high-k gate dielectric device; long channel transistor; poly deletion; system-on-chip applications; threshold voltage; ultra low power applications; Annealing; Boron; Doping; Fabrication; High-K gate dielectrics; Implants; Large scale integration; Leakage current; SRAM chips; Threshold voltage;
Conference_Titel :
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8289-7
DOI :
10.1109/VLSIT.2004.1345380