MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

Author

Pidin, S. ; Mori, T. ; Nakamura, R. ; Saiki, T. ; Tanabe, R. ; Satoh, S. ; Kase, M. ; Hashimoto, K. ; Sugii, T.

Author_Institution

Adv. LSI Dev. Div., Fujitsu Ltd., Tokyo, Japan

fYear

2004

Firstpage

54

Lastpage

55

Abstract

NMOSFET strain engineering using highly tensile silicon nitride capping layer was studied by way of extensive numerical simulations and device experiments. At 45nm gate length and 1V supply voltage fabricated NMOSFET delivers 1.00mA/ μm drive current for off-state current of 40nA/ μm and physical gate oxide thickness of 1.25nm(TEM). These data demonstrate the best up to date NMOSFET current drivability. Next, using extensive process simulations to analyze fabricated devices we developed optimization guidelines for NMOSFET strain engineering enabling us further improvement of device current drivability with reducing the gate length.

Keywords

MOSFET; silicon compounds; 1.25 nm; 45 nm; 65 nm; MOSFET current drive optimization; SiN; SiN capping layer; gate length; process simulations; Capacitive sensors; Guidelines; Implants; Laboratories; Large scale integration; MOSFET circuits; Silicon compounds; Tensile strain; Tensile stress; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345389

Filename

1345389