Automatic VHDL synthesizability checking based on the user-defined rules for ASIC design

The development of an automatic VHDL synthesizability checker (VSC) for an ASIC design VSC helps an ASIC designer to confirm the synthesizability of a VHDL model in the early stage of design, even before the simulation. Unlike a checker within a synthesizer, VSC performs the checking process based on the user-defined synthesis rule set. VSC provides an ASIC designer with flexible control over the checking process. It also allows a designer to handle the different synthesizable VHDL subsets