Title :
Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs
Author :
Ueki, M. ; Narihiro, M. ; Ohtake, H. ; Tagami, M. ; Tada, M. ; Ito, F. ; Harada, Y. ; Abe, M. ; Inoue, N. ; Arai, K. ; Takeuchi, T. ; Saito, S. ; Onodera, T. ; Furutake, N. ; Hiroi, M. ; Sekine, M. ; Hayashi, Y.
Author_Institution :
Syst. Devices Res. Labs, NEC Corp., Sagamihara, Japan
Abstract :
Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nmφ-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a "DD pore seal" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with keff ∼3.0 is applicable especially for the 65nm-node, low-power ASICs.
Keywords :
application specific integrated circuits; copper; integrated circuit interconnections; integrated circuit reliability; nanotechnology; 180 nm; 200 nm; 65 nm; 65 nm-node Cu dual damascene interconnects; Cu; Cu agglomeration; DDI via-yield; dielectric reliability; full porous-SiOCH films; low thermal-budget process; low-power ASICs; Application specific integrated circuits; Costs; Dielectric constant; Etching; Indium tin oxide; National electric code; Power dissipation; Seals; Temperature; Thermal resistance;
Conference_Titel :
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8289-7
DOI :
10.1109/VLSIT.2004.1345393
