Title :
FFT processor using field programmable gate arrays
Author :
Botros, N. ; Zakhem, W.
Author_Institution :
Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
The design and construction of a hardware fast Fourier transform processor are presented. The hardware relies principally on field programmable gate arrays (FPGAs). The hardware architecture is based on Tukey-Cooley butterfly algorithms. It uses 218 configurable logic blocks (CLBs) and 42 input-output processors (IOBs) and implements a simple parallel processing architecture. The input of the processor is 16 real-value points and the output is complex. The execution time of the transform is estimated to be 0.736 ms
Keywords :
digital signal processing chips; fast Fourier transforms; logic arrays; parallel architectures; 0.736 ms; FFT processor; Tukey-Cooley butterfly algorithms; configurable logic blocks; field programmable gate arrays; input-output processors; parallel processing architecture; real-value points; Acceleration; Biomedical engineering; Costs; Equations; Fast Fourier transforms; Field programmable gate arrays; Hardware; Image processing; Parallel processing; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270295
