DocumentCode :
1608700
Title :
Performance estimation in MPSoC design with SDF graphs
Author :
Smiri, K. ; Jemai, A.
Author_Institution :
LIP2 Lab., Univ. of Tunis El Manar, Tunis, Tunisia
fYear :
2012
Firstpage :
189
Lastpage :
194
Abstract :
Multi-Processor Systems-on-Chip (MPSoC) are going to be the leading hardware platform featured in embedded systems, if they aren´t already. This article deals with the performance estimation problem on these systems. Its purpose is the validation of a performance estimation methodology, proposed by the LIP2 laboratory (Tunis Faculty of Sciences, Tunis, Tunisia). Using the SDF3 tool, we modeled (1) a multimedia application using SDF graphs, (2) a target NoC-MPSoC platform, and (3) a performance constraint of 25 frames per second. With the same tool, we executed several static analyses to estimate the performances of the application (1) when ran on the target platform (2). Two approaches were adopted that are described in further details: graph transformation and processor specialization.
Keywords :
embedded systems; graph grammars; multimedia computing; multiprocessing systems; performance evaluation; system-on-chip; MPSoC design; NoC-MPSoC platform; SDF graph; SDF3 tool; embedded system; graph transformation; hardware platform; multimedia application; multiprocessor systems-on-chip; performance constraint; performance estimation; processor specialization; static analysis; Decoding; Estimation; Hardware; Protocols; Software; Throughput; Tiles; MPSoC; Multimedia Application; NoC-MPSoC; SDF graphs; SDF3 tool; Software-to-Hardware migration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Sciences of Electronics, Technologies of Information and Telecommunications (SETIT), 2012 6th International Conference on
Conference_Location :
Sousse
Print_ISBN :
978-1-4673-1657-6
Type :
conf
DOI :
10.1109/SETIT.2012.6481911
Filename :
6481911
Link To Document :
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