A new low-power N fold flip-flop with output enable

Flip-flops with output enable are crucial elements for the design of digital systems. With the aggressive scaling in feature sizes, they start to pose some challenging problems for designers. This is due to their synchronous nature that represents the main cause of both the high digital noise that they generate and the significant fraction of power that they consume essentially dynamically. In this paper we delve into the design of n-fold flip-flops with output enable. A new n-fold flip-flop exploiting the clock gating technique for both outputs enabling and power saving is presented. To evaluate its performance, an octal flip-flop was built according to the new proposed structure and compared to the main octal flip-flops used today. The different flip-flops were implemented in STMicroelectronics 65 nm process technology and simulated for the worst case condition where the switching activity is maximal. Post layout simulation showed that the new circuit provides the same functional performances as conventional solutions with significantly less power consumption, area and digital noise.