DocumentCode
1608756
Title
4B5B decoder for FDDI
Author
Wronski, Leszek D. ; Albicki, Alexander
Author_Institution
Dept. of Electr. Eng., Rochester Univ., NY, USA
fYear
1992
Firstpage
83
Lastpage
86
Abstract
A 2-μm CMOS FDDI (fiber distributed data interface) 4B5B decoder with an elastic self-timed buffer is presented. The design operates at 125 MHz and meets the requirements specified by the ANSI X3.139-1987 standard. The characteristic features of this design are logical simplicity, compact silicon area, operational speed well above that specified for FDDI, and metastable operation resistivity. These features have been obtained by self-timed implementation of the elastic buffer
Keywords
CMOS integrated circuits; FDDI; buffer circuits; decoding; optical communication equipment; 125 MHz; 4B5B decoder; ANSI X3.139-1987 standard; CMOS; FDDI; elastic self-timed buffer; fiber distributed data interface; metastable operation resistivity; operational speed; ANSI standards; CMOS technology; Clocks; Decoding; Delay; FDDI; Frequency synchronization; Optical buffering; Packaging; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270301
Filename
270301
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