Vertical floating-gate 4.5F/sup 2/ split-gate NOR flash memory at 110nm node

Author

Lee, Yeeheng ; Tsui, Felix ; Yang, Jeng-Wei ; Gao, Feng ; Lu, Wen-Juei ; Yeeheng Lee ; Chi-Tsai Chen ; Huang, Vincent ; Wang, Pin-Yao ; Liu, M.H. ; Hsu, Yaw-Wen ; Chang, Simon ; Chang, S.Y. ; Van Tran, Hieu ; Frayer, Jack ; Yaw-Wen Hu ; Yeh, Bing ; Chen,

Author_Institution

Silicon Storage Technol. Inc., Sunnyvale, CA, USA

fYear

2004

Firstpage

72

Lastpage

73

Abstract

We present the structural and electrical characteristics of the latest generation of a self-aligned split-gate NOR memory incorporating a vertical floating-gate channel having 4.5F/sup 2/ area on 110 nm half-pitch rules. With enhanced electric fields for erase and programming, the cell achieves erase time < 1 ms and program time < 10 /spl mu/s at 100nA programming current. These results demonstrate continued scalability of the SuperFlash cell for high-density, high-speed applications.

Keywords

flash memories; logic gates; 10 mus; 100 nA; 110 nm; 110nm node; continued scalability; electrical characteristics; enhanced electric fields; erase; programming; structural characteristics; vertical floating-gate 4.5F/sup 2/ split-gate NOR flash memory; Character generation; Electrons; Flash memory; Hot carriers; Nonvolatile memory; Split gate flash memory cells; Tungsten; Tunneling; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345400

Filename

1345400