A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

Author

Yasutake, N. ; Ohuchi, K. ; Fujiwara, M. ; Adachi, K. ; Hokazono, A. ; Kojima, K. ; Aoki, N. ; Suto, H. ; Watanabe, Toshio ; Morooka, T. ; Mizuno, Hidenori ; Magoshi, S. ; Shimizu, T. ; Mori, S. ; Oguma, H. ; Sasaki, T. ; Ohmura, M. ; Miyano, K. ; Yamada,

Author_Institution

SoC Res. & Dev. Center, Toshiba Corp., Kanagawa, Japan

fYear

2004

Firstpage

84

Lastpage

85

Abstract

High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V_dd condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f_i is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; incoherent light annealing; silicon compounds; 10 nm; 1706 mS/mm; 22 nm; 400 GHz; SRAM performance; elevated source/drain extension; flash lamp annealing; fully silicided metal gate; high transconductance; hp22 nm node low operating power technology; key process; optimization method; planar MOSFET structure; sub-10 nm gate length planar bulk CMOS devices; CMOS technology; CMOSFETs; Degradation; Electrodes; MOS devices; MOSFET circuits; Manufacturing processes; Optimization methods; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345407

Filename

1345407