An implementation of a clock-tree distribution scheme for high-performance ASICs

An implementation of a multilevel balanced clock-tree distribution scheme that improves the performance of ASICs considerably is described. Layout process and the CAD tools are briefly described, and the results are tabulated for differing complexities of real customer designs. The focus of this clock-tree distribution scheme is on minimizing the clock skew, on reducing the total clock delay from the clock driver to a clock pin, on improving rise/fall times, and on minimizing the silicon area consumed by the clock circuitry