Dependability validation of a cryptoprocessor to SEU effects

This paper presents the results of the dependability validation of a cryptoprocessor to SEU effects. The dependability validation was carried out running a testbench, initially using functional simulation, and later using in-system hardware execution. For the fault injection, a modified memory cell and a strategy of pseudorandom generation of states into FSMs are proposed. The testbench was simulated using Modelsim, and was executed on the FPGA EP2S601020C4 and the results are observed using an Embedded Logic Analyzer. The simulation and experimental results show that registers and FSMs require to be hardened in order to warrantee the correct operation of the cryptoprocessor, also the in-system hardware execution of the testbench allows to speed up more than 1000 times the dependability validation step.