A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

Author

Ranica, R. ; Villaret, A. ; Malinge, P. ; Mazoyer, P. ; Lenoble, D. ; Candelier, P. ; Jacquet, F. ; Masson, P. ; Bouchakour, R. ; Fournel, R. ; Schoellkopf, J.P. ; Skotnicki, T.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2004

Firstpage

128

Lastpage

129

Abstract

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25°C and 100ms at 85°C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85°C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.

Keywords

CMOS logic circuits; DRAM chips; system-on-chip; 1 s; 100 ms; 25 degC; 85 degC; CMOS logic process integration; SoC applications; high density eDRAM; low-cost DRAM; one transistor cell; very low chip cost; CMOS process; Dynamic programming; Energy consumption; Impact ionization; Logic devices; MOSFET circuits; Performance evaluation; Silicon; Voltage; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345433

Filename

1345433