DocumentCode
1609608
Title
Highly scalable FBC (Floating Body Cell) with 25nm BOX structure for embedded DRAM applications
Author
Shino, Tomoaki ; Higashi, Tomoki ; Fujita, Katsuyuki ; Ohsawa, Takashi ; Minami, Yoshihiro ; Yamada, Takashi ; Morikado, Mutsuo ; Nakajima, Hiroomi ; Inoh, Kazumi ; Hamamoto, Takeshi ; Nitayama, Akihiro
Author_Institution
SoC Res. & Dev. Center, Toshiba Corp., Yokohama, Japan
fYear
2004
Firstpage
132
Lastpage
133
Abstract
A novel FBC with 25nm-thick BOX (buried oxide) structure has been developed. A feature of new FBC is scalability in the case of thinner SOI, which promises embedded DRAM on SOI in future generations. Using 96Kbit array, the pause time distribution of FBC is demonstrated for the first time. Due to simplified structure, pause time variation of new FBC is significantly suppressed compared with conventional FBC.
Keywords
DRAM chips; buried layers; silicon-on-insulator; 25 nm; 25nm BOX structure; embedded DRAM applications; floating body cell; pause time distribution; CMOS process; Capacitance; Capacitors; Electric variables; Impact ionization; Microelectronics; Random access memory; Research and development; Scalability; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN
0-7803-8289-7
Type
conf
DOI
10.1109/VLSIT.2004.1345435
Filename
1345435
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