Author :
Kanaya, H. ; Tomioka, K. ; Matsushita, T. ; Omura, Mototsugu ; Ozaki, T. ; Kumura, Y. ; Shimojo, Y. ; Morimoto, Takuya ; Hidaka, O. ; Shuto, S. ; Koyama, H. ; Yamada, Y. ; Osari, K. ; Tokoh, N. ; Fujisaki, F. ; Iwabuchi, N. ; Yamaguchi, Naoto ; Watanabe,
Author_Institution :
Semicond. Co., Toshiba Corp., Yokohama, Japan
Abstract :
We have successfully developed a 0.602 μm2 nestled ´Chain´ FeRAM cell technology for 64Mbit FeRAM. In the ´Chain´ FeRAM a pair of capacitors on a same node can be nestled close to each other A combination of a one mask etching process of ferro-electric capacitors and the nestled structure drastically scaled down the cell size to 0.602 μm2. The cell size was reduced to 32% of previous work. Signal window of 600 mV was obtained by the nestled ´Chain´ FeRAM structure after full integration of three-metal CMOS technology.
Keywords :
CMOS integrated circuits; ferroelectric capacitors; ferroelectric storage; 600 mV; 64 Mbit; 64 Mbit FeRAM; ferroelectric capacitors; mask etching process; nestled chain cell structure; three-metal CMOS technology; Annealing; CMOS technology; Capacitors; Electrodes; Etching; Ferroelectric films; Nonvolatile memory; Plugs; Random access memory; Signal processing;
