A pipelined ADC design exploration methodology employing circuit-system refinement

A pipelined ADC equation-based design space exploration methodology targeting minimum power dissipation is presented. While distinct frontiers are drawn between system-level and circuit-level design phases, this paper shows the importance of a refinement step between both phases. At the system-level, all possible architectures are examined followed by behavioral validation. Using a circuit sizing tool, different circuit topologies are investigated. The refinement phase proves to be important to increase the accuracy of system-level calculations by remapping new circuit-related parameters using the achieved circuit performances. The flow was built in an open system environment where the user has the freedom to change the modeling approach at any level, introduce different equations, and relax/tighten design constraints. An 11-bit ADC design test case is given to illustrate the methodology.