DocumentCode
1610219
Title
New guideline of Vdd and Vth scaling for 65nm technology and beyond
Author
Morifuji, E. ; Yoshida, T. ; Tsuno, H. ; Kikuchi, Y. ; Matsuda, S. ; Yamada, S. ; Noguchi, T. ; Kakumu, M.
Author_Institution
Syst. LSI Div., Toshiba Corp., Yokohama, Japan
fYear
2004
Firstpage
164
Lastpage
165
Abstract
We show new guideline of Vdd and Vth scaling for logic blocks and high density SRAM cell from low power dissipation viewpoint. New degradation mode for inverter delay becomes major obstacle for Vdd scaling in the future. Low Vdd and low Vth should be applied only for circuits with high switching activity. In other portions, Vdd should be kept around 1-1.2V. High density SRAM with beta ratio of 1(0.56 μm2) operates at 0.7V by choosing optimum Vth.
Keywords
CMOS integrated circuits; CMOS logic circuits; 65nm technology; high density SRAM cell; high switching activity; inverter delay; logic blocks; low power dissipation viewpoint; Circuits; Degradation; Delay; Energy consumption; Frequency; Guidelines; Logic; Power dissipation; Random access memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN
0-7803-8289-7
Type
conf
DOI
10.1109/VLSIT.2004.1345457
Filename
1345457
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