Implementation and evaluation of microinstruction controlled self test using a masked microinstruction scheme

Author

Nozuyama, Y. ; Nishimura, A. ; Iwamura, J.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1989

Firstpage

625

Lastpage

632

Abstract

A masked microinstruction scheme which reduces the size of the test microprogram used for a microinstruction-controlled self-test, a type of built-in self-test, is described. Implementation of the scheme applied to a 32-b microprocessor, the TX1, is illustrated, and its efficiency is discussed. Over 95% fault coverage for data path blocks in an execution unit is achieved, and almost all related control logic is tested with about 600 steps of test microprogram in the TX1. Without the scheme, it is estimated that the equivalent test requires about 1200 steps. Applicability of the scheme to other types of microprocessors is also discussed

Keywords

automatic testing; computer testing; integrated circuit testing; microprocessor chips; microprogramming; 32 bits; IC testing; TX1; VLSI; built-in self-test; computer testing; data path blocks; fault coverage; masked microinstruction scheme; microinstruction controlled self test; microprocessor chips; test microprogram; Automatic testing; Built-in self-test; Decoding; Hardware; Logic testing; Microprocessors; Read only memory; Semiconductor device testing; Semiconductor devices; Size control;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82256

Filename

82256