Title :
Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping
Author :
Lallement, F. ; Duriez, B. ; Grouillet, A. ; Arnaud, F. ; Tavel, B. ; Wacquant, F. ; Stolk, P. ; Woo, M. ; Erokhin, Y. ; Scheuer, J. ; Godet, L. ; Weeman, J. ; Distaso, D. ; Lenoble, D.
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
N-type and p-type Plasma Doping (PLAD) process have been developed for fabricating the ultra-shallow junctions (USJ) needed for the 65nm CMOS technology. For the first time, the strong benefit of PLAD compared to ultra-low energy implantations for fabricating sub-25nm USJ is demonstrated when standard activation technique is used. Such plasma-doped USJ were successfully integrated into a conventional 65nm CMOS architecture (no offset spacers, low ramp-rate spike annealing <75°C/s) for the Source-Drain Extensions (SDE) doping. Transistors drive currents of 720 μA/μm and 330 μA/μm for NMOS and PMOS respectively are obtained at Vdd=0.9V, Ioff=100 nA/ μm. In addition, junction leakage current was significantly improved (>1 decade) and junction capacitance was reduced by 15% for NMOS.
Keywords :
CMOS integrated circuits; annealing; nanotechnology; plasma immersion ion implantation; semiconductor doping; 65 nm; 65nm CMOS device; junction leakage current; plasma doping; ultra-low energy implantations; ultra-shallow junctions; Annealing; CMOS process; CMOS technology; Costs; Doping; Leakage current; MOS devices; Plasma devices; Plasma sources; Space technology;
Conference_Titel :
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8289-7
DOI :
10.1109/VLSIT.2004.1345465
