Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping

N-type and p-type Plasma Doping (PLAD) process have been developed for fabricating the ultra-shallow junctions (USJ) needed for the 65nm CMOS technology. For the first time, the strong benefit of PLAD compared to ultra-low energy implantations for fabricating sub-25nm USJ is demonstrated when standard activation technique is used. Such plasma-doped USJ were successfully integrated into a conventional 65nm CMOS architecture (no offset spacers, low ramp-rate spike annealing <75°C/s) for the Source-Drain Extensions (SDE) doping. Transistors drive currents of 720 μA/μm and 330 μA/μm for NMOS and PMOS respectively are obtained at V_dd=0.9V, I_off=100 nA/ μm. In addition, junction leakage current was significantly improved (>1 decade) and junction capacitance was reduced by 15% for NMOS.