DocumentCode :
1610785
Title :
Redundancy identification using transitive closure
Author :
Agrawal, Vishwani D. ; Bushnell, Michael L. ; Lin, Qing
Author_Institution :
Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
fYear :
1996
Firstpage :
4
Lastpage :
9
Abstract :
We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higher-order terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuck-at faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuck-at faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuck-at faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuck-at fault is redundant. We give ISCAS ´85 benchmark results. For c6288, we could identify 31 out of 33 redundancies. The percentage of identified redundancies was not always that high, but the algorithm has polynomial complexity and we discuss its limitations
Keywords :
Boolean functions; automatic test software; binary sequences; circuit analysis computing; combinational circuits; computability; computational complexity; fault diagnosis; fault location; logic testing; observability; redundancy; signal flow graphs; ATPG; Boolean equations; ISCAS ´85 benchmark results; binary variables; combinational circuit; false observability status; fault-independent method; graph algorithm; higher-order terms; implication graph; logic value; observability status; one-pass method; pairwise terms; polynomial complexity; redundancy identification; signal assignments; stuck-at faults; transitive closure; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Equations; Fault diagnosis; Observability; Redundancy; Sequential circuits; Signal analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
ISSN :
1085-7735
Print_ISBN :
0-8186-7478-4
Type :
conf
DOI :
10.1109/ATS.1996.555127
Filename :
555127
Link To Document :
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