Channel design and mobility enhancement in strained germanium buried channel MOSFETs

Author

Shang, H. ; Chu, J.O. ; Wang, X. ; Mooney, P.M. ; Lee, K. ; Ott, J. ; Rim, K. ; Chan, K. ; Guarini, K. ; Ieong, M.

Author_Institution

Semicond. Res. & Dev. Center, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2004

Firstpage

204

Lastpage

205

Abstract

In this work, the channel design space for scaled strained Ge (s-Ge) buried channel (BC) MOSFETs is examined by simulations and experiments. The identified Ge channel layer structure is scalable to sub-30nm devices. Furthermore, strained Ge buried-channel MOSFETs with an ultra thin (1.5nm) Si cap are demonstrated with a 6× hole mobility enhancement over the Si universal hole mobility. Compared with surface channel Ge MOSFETs. buried strained Ge channel structures can be integrated with fewer processing challenges to achieve a significantly enhanced hole mobility and an improved electron mobility.

Keywords

MOSFET; carrier mobility; elemental semiconductors; germanium; 1.5 nm; 30 nm; Ge; channel design; hole mobility enhancement; mobility enhancement; strained Ge buried channel MOSFETs; surface channel; universal hole mobility; Buffer layers; CMOS technology; Carrier confinement; Doping profiles; Electron mobility; Germanium silicon alloys; MOSFETs; Silicon germanium; Strain measurement; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345480

Filename

1345480