Enhancing the Grid Alu processor for a better exploitation of the functional units

Current emerging reconfigurable coarse grained processors are gaining more popularity, as they introduce a new way for more dynamicity similar to FPGA and tend to achieve the performance of application specific hardware. An adaptive architecture can face the diversity of applications dynamically in the hardware without the need of any software manipulation. However the need for more flexibility to manage the underlying hardware structures increases the demands on the configuration hardware unit. Managing the hardware resources in the software however prevents undertaking many dynamical reactions needed by the reconfiguration task at runtime to be adaptive to the dynamic program execution. This paper presents an improvement of the configuration unit for the Grid Alu Processor that automatically reconfigures instructions to an array of reconfigurable functional units. The mapping task is improved to be aware of the utilization of functional units and data dependencies of instructions. The simulation of a better utilized grid has shown an improvement in the performance for up to the factor of 1.2 compared to the basic mapping mechanism and up to 2.2 compared to the out-of-order SimpleScalar simulator.