Title :
SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors
Author :
Tamura, Y. ; Sasaki, T. ; Izumi, N. ; Ootsuka, F. ; Yasuhira, M. ; Hoshi, T. ; Kume, S. ; Amai, H. ; Ida, T. ; Aoyama, T. ; Kamiyama, S. ; Torii, K. ; Kitajima, H. ; Arikado, T.
Author_Institution :
Semicond. Leading Edge Technol., Inc., Ibaraki, Japan
Abstract :
This paper describes the SiN-capped HfSiON gate stacks for 65 nm-node low-standby-power transistors with improved bias temperature instabilities (BTI). By employing SiN-cap on HfSiON and the counter-implant for adjustment of pFET´s threshold voltage (VTH), the symmetrical VTH values for nFETs and pFETs have been obtained. The nitrogen incorporation in the interfacial oxide prevents the interface states generation under positive bias temperature stress. Negative BTI can be improved by reducing the thickness of SiN-cap. 10-year lifetimes for both positive and negative BTI have been achieved.
Keywords :
CMOS integrated circuits; VLSI; hafnium compounds; insulating thin films; interface states; power MOSFET; silicon compounds; 65 nm; 65 nm-node low-standby-power transistors; SiN-HfSiON; SiN-capped HfSiON gate stacks; improved bias temperature instabilities; interfacial oxide; threshold voltage; High K dielectric materials; High-K gate dielectrics; Interface states; Lead compounds; Nitrogen; Silicon compounds; Stress; Temperature; Threshold voltage; Virtual manufacturing;
Conference_Titel :
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8289-7
DOI :
10.1109/VLSIT.2004.1345484
