FPGA implementation of modified architecture for adaptive Viterbi decoder

The demand for high speed, low power and low cost for Viterbi decoding especially in wireless communication are always required. Thus the paper presents the design of an adaptive Viterbi decoder that uses survivor path with parameters for wireless communication in an attempt to reduce the power and cost and at the same time increase the speed. The decoder was simulated using MATLAB 7. In the simulation the BER is calculated and compared with the other models. Furthermore, the system operation under high frequency conditions is also investigated. Next a VHDL description has been adopted to embed the low-power design. The adopted design were coded in VHDL and implemented on a SPARTAN 3. The results show that speed has been increased since the the processing execution time has been reduced by removing the trace back algorithms that is used to find the correct paths. Furthermore, the survivor path decoder is capable of supporting frequency up to 790 MHz for constraint lengths 7, and 9, rate 1/3 and long survivor path is 4. Finally, the cost has been reduced since the different constraint length didn´t affect of the complexity of the decoder and the processing time of computing the correct path.