Stress-induced context-variability in digital design

As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. Therefore the stress-based extraction flow has become a candidate to accurately capture the process variations. This paper presents a proposal for a software framework to enhance the manufacturability of the traditional standard cell library. The novel method comprises fully automated stress-aware techniques for measuring timing variations in digital cells. The results indicate a ±6% variation across whole library contexts with respect to mean value.