PVT-variations-tolerant clock design using self-correcting adjustable delay buffers

As the process technology scaling, the tolerance to PVT (process/ voltage/temperature) variation has become a serious concern. During the post-silicon stage, ADBs (adjustable delay buffers) can be used to adjust the delay of the clock path for eliminating the clock skew. However, in fact, unless that the clock tree has a self-correcting mechanism, the clock skew caused by PVT variations still cannot be properly controlled. In this paper, we propose the first self-correcting ADB system to control the clock skew during circuit execution. Experimental results show that our design methodology can achieve very good results.