Title :
Hierarchical test generation with built-in fault diagnosis
Author :
Stroobandt, Dirk ; Van Campenhout, Jan
Author_Institution :
Dept. of Electron. & Inf. Syst., Ghent Univ., Belgium
Abstract :
A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from the start. An efficient test compaction method leads to a very compact test set, while retaining a maximum of diagnostic power and a 100% fault coverage for non-fanout circuits. An extension for fanout circuits is also presented
Keywords :
VLSI; application specific integrated circuits; automatic testing; fault diagnosis; integrated circuit testing; logic testing; ASIC; VLSI; built-in fault diagnosis; diagnostic power; fanout circuits; fault coverage; hierarchical test generation; inherent hierarchical structure; nonfanout circuits; test compaction method; Automatic testing; Circuit faults; Circuit testing; Combinational circuits; Compaction; Electronic equipment testing; Fault diagnosis; Flip-flops; Sequential analysis; System testing;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555130
