• DocumentCode
    1611745
  • Title

    InP HBT XOR and phase-detector for 40 Gbit/s clock and data recovery (CDR)

  • Author

    Puyal, V. ; Konczykowska, A. ; Riet, M. ; Bernard, S. ; Nouet, P. ; Godin, J.

  • Author_Institution
    Alcatel-Thales III-V Lab, Marcoussis
  • fYear
    2006
  • Firstpage
    1115
  • Lastpage
    1118
  • Abstract
    High-speed XOR and phase-detector circuit necessary for clock and data recovery were designed and fabricated in a self-aligned InP DHBT technology. In the paper, we present the circuit design with the special highlight of the architecture choice and design challenges. Measurements results of fabricated circuits are shown.
  • Keywords
    heterojunction bipolar transistors; phase detectors; synchronisation; CDR; InP DHBT XOR; bit rate 40 Gbit/s; circuit design; clock-data recovery; double heterojunction bipolar transistor technology; phase-detector; Circuit synthesis; Clocks; DH-HEMTs; Frequency; Heterojunction bipolar transistors; Indium gallium arsenide; Indium phosphide; Optical receivers; Optical transmitters; Time division multiplexing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microwaves, Radar & Wireless Communications, 2006. MIKON 2006. International Conference on
  • Conference_Location
    Krakow
  • Print_ISBN
    978-83-906662-7-3
  • Type

    conf

  • DOI
    10.1109/MIKON.2006.4345382
  • Filename
    4345382
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1611745