A new interface-trapped-charge-degraded subthreshold current model for cylindrical, surrounding-gate (CSRG) MOSFETs

ITRS has revealed that the implantation of non-classical CMOS structures are needed to overcome the difficult challenges when the semiconductor technology node is below 16nm. It also indicates that the multiple-gate (MG) MOSFETs with the strong field confinement, prominent volume conduction, and high packing density can be the promising candidates for the future CMOS application. The novel structures for the surrounding-gate (SRG) MOSFETs with the high performance and scalability can be used for the memory DRAM cell [1]. To utilize this device for the memory cell application, it is mandatory to develop a feasible model. Although a numerous of literatures have modeled the drain current for the MG devices [2][3], there are no investigations on the subthreshold current model for the cylindrical, surrounding-gate (CSRG) MOSFETs with the interface trapped charges. In this paper, by accounting for the effects of interface trapped charges on the flat-band voltage, we propose a compact sub-threshold current model for the CSRG MOSFETs with the interface trapped charges based on the scaling equation and drift-diffusion approach. The proposed model explicitly illustrates how the interface trapped charges with different polarities, damaged zone lengths, gate oxide, and silicon body thicknesses affect the subthreshold current degradation. The model can be used to explore the hot-carrier-induced sub-threshold current degradation for the CSRG MOSFET for its memory device application.