A 0.5–6GHz low gain linear RF front-end in 90nm CMOS

This paper presents the design and measurement results of low gain RF front-end manufactured in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transconductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match better than -8dB up to 8GHz. The voltage conversion gain is 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz. Similarly, measured IIP3 is 2.5dBm and IIP2 is 40dBm at 1GHz. The complete front-end consumes 23mW with active chip area of only 0.048mm².