CMOS integration issues with high-k gate stack

Continual CMOS scaling requires the implementation of high-k gate dielectrics with metal gate to alleviate the rapid gate tunneling current increase associated with aggressive EOT scaling. The purpose of this paper is to review some of the integration challenges that high-k/metal gate stack technology is facing. This includes thermal stability of high-k against crystallization, phase separation, and interfacial reaction with underlying Si, charges/traps in high-k as well as at interfaces, channel carrier mobility degradation, EOT control and scaling, work function control for dual-gate CMOS integration, and gate stack reliability. The engineering of the high-k/Si as well as metal/high-k interfaces is identified as the most important factor for achieving EOT<<1 nm with good performance and reliability.