Title :
CMOS integration issues with high-k gate stack
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
Continual CMOS scaling requires the implementation of high-k gate dielectrics with metal gate to alleviate the rapid gate tunneling current increase associated with aggressive EOT scaling. The purpose of this paper is to review some of the integration challenges that high-k/metal gate stack technology is facing. This includes thermal stability of high-k against crystallization, phase separation, and interfacial reaction with underlying Si, charges/traps in high-k as well as at interfaces, channel carrier mobility degradation, EOT control and scaling, work function control for dual-gate CMOS integration, and gate stack reliability. The engineering of the high-k/Si as well as metal/high-k interfaces is identified as the most important factor for achieving EOT<<1 nm with good performance and reliability.
Keywords :
CMOS integrated circuits; carrier mobility; crystallisation; dielectric thin films; electron traps; integrated circuit metallisation; integrated circuit reliability; phase separation; thermal stability; CMOS scaling; EOT control; EOT scaling; channel carrier mobility degradation; charges/traps; crystallization; dual-gate CMOS; gate stack reliability; gate tunneling current; high-k gate dielectrics; high-k gate stack CMOS integration; interfacial reaction; metal gates; metal/high-k interfaces; phase separation; thermal stability; work function control; Annealing; Crystallization; Electrodes; High K dielectric materials; High-K gate dielectrics; MOS devices; Robust stability; Temperature; Thermal degradation; Thermal stability;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN :
0-7803-8454-7
DOI :
10.1109/IPFA.2004.1345524
