A study of regular architectures for digital implementation of neural networks

Investigations making use of a regular processor architecture for multilayer neural networks (NNs) are described. By comparing bus-coupling, ring, and mesh topologies, the authors theoretically analyzed the required data transmission count and calculation count for one iteration of training for a NN with one hidden layer. For a minimum data transmission count, an optimal number of processor elements (PEs) exists in the case of mesh, whereas no global optimum occurs for the bus-coupling and ring topologies. The minimum total computation count obtained by the mesh is less than 1/6 (1/30) of the ring (bus-coupling). The investigation also includes the relation of PE performance and computation time, in which the bit-serial design is compared to the bit-parallel. An example of a block description of a PE for the mesh topology is described