A Time-constrained Watermarking Technique on FPGA

The digital integrated circuits are becoming more and more complicated, the concept of design reuse has been widely accepted by the designers. However, the design reuse also makes rival competitor easier to infringe the intellectual properties (IPs). IP protection becomes a crucial work of IP reuse design style. This paper proposes a method for IP protection based on modification of time constraints. We select non-critical nets as watermark carrier and embed a watermark by modifying time constraints. Thus the FPGA configuration bit stream for the resulting watermarked design will be significantly different from the original design, which provides a strong proof of authorship. The watermarking technique has zero area overhead and low timing overhead, also effectively increases the embedding capacity of watermark simultaneously. We evaluated the method on ISCAS´89 benchmark. Compared to reference [4], our technique improved the watermarking performance.