Dielectric-breakdown-induced epitaxy: a universal breakdown defect in ultrathin gate dielectrics

The breakdown phenomena in SiO_xN_y (EOT=20 Å) gate dielectric, under a two-stage constant voltage stress in inversion mode, are physically analyzed with the aid of high resolution transmission electron microscopy. The results show that dielectric-breakdown-induced epitaxy (DBIE) remains as one of the major failure defects responsible for gate dielectric breakdown evolution even for a stress voltage as low as 2.5 V. Based on the results, the same failure mechanism i.e., presence of DBIE would be responsible for the degradation in ultrathin gate dielectrics for gate voltages below 2.5 V. It is believed that DBIE will be present in MOSFETs failed at nominal operating voltage.