A new very high speed CMOS 4−2 compressor for fast digital arithmetic circuits

This paper presents a new technique for realizing very high-speed CMOS 4-2 compressor which is an essential part in fast digital arithmetic integrated circuits. We have used current mode fully differential circuit technique for designing the compressor circuit. The proposed compressor has been compared to a conventional and a high speed dual-pass transistor logic (DPL) structures. For a fair comparison all of the circuits have been simulated in 0.18μm standard TSMC CMOS process with 1.8V power supply voltage. Post layout simulation results show that our proposed circuit improves speed up to 45% also improves area in comparison to other high-speed conventional compressor circuits. Worst-case delay of the proposed compressor is 210ps with power consumption of 190μW. Active area is 13μm × 59μm.