Title :
Modeling of wearout, leakage, and breakdown of gate dielectrics [MOSFET]
Author :
Gehring, A. ; Selberherr, S.
Author_Institution :
Inst. for Microelectron., Tech. Univ. of Vienna, Austria
Abstract :
We present a set of models for the simulation of gate dielectric wearout, leakage, and breakdown. Wearout is caused by the leakage-induced creation of neutral defects at random positions in the dielectric layer, which, if occupied, degrade the threshold voltage of the device. Leakage is due to direct and trap-assisted tunneling through these defects. Finally, gate dielectric breakdown is triggered by the formation of a conductive path through the insulator. To allow the trap characterization, and for the simulation of fast transients, the modeling of trap charging and discharging processes is outlined. The model has been implemented into a 3D device simulator and is used for the characterization. of ZrO2-based dielectrics and for the study of gate leakage and wearout effects in standard CMOS inverter circuits.
Keywords :
MOSFET; dielectric thin films; leakage currents; semiconductor device breakdown; semiconductor device models; transient response; tunnelling; zirconium compounds; CMOS inverter circuits; MOSFET; ZrO2; dielectric breakdown; dielectric leakage; direct tunneling; fast transients; gate dielectric wearout; neutral defect leakage-induced creation; threshold voltage degradation; through-insulator conductive path formation; trap charging; trap discharging; trap-assisted tunneling; Circuit simulation; Degradation; Dielectric breakdown; Dielectric devices; Dielectrics and electrical insulation; Gate leakage; MOSFET circuits; Semiconductor device modeling; Threshold voltage; Tunneling;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Print_ISBN :
0-7803-8454-7
DOI :
10.1109/IPFA.2004.1345540
