Title :
CLASS: a CAD system for automatic synthesis and verification of asynchronous finite state machines
Author_Institution :
Cirrus Logic, Fremont, CA, USA
Abstract :
The author describes algorithms and techniques underlying a CAD system called CLASS (Cirrus Logic Asynchronous Synthesis System) for automatic synthesis and verification of control circuits based on asynchronous finite state machine (AFSM) specifications. AFSM specifications are transformed into signal transition graphs and then to state graphs. Newly developed hazard-free synthesis techniques from state graphs are described. An efficient two-level hierarchical verification technique based on state graph contraction and Dill´s verifier is used to verify the logic implementations against the state graph.
Keywords :
asynchronous sequential logic; finite state machines; hazards and race conditions; logic CAD; CAD system; CLASS; Cirrus Logic Asynchronous Synthesis System; asynchronous finite state machine; hazard-free synthesis; hierarchical verification technique; signal transition graphs; state graphs; verification; Automata; Automatic control; Automatic logic units; Circuit synthesis; Control system synthesis; Delay; Logic circuits; Logic design; Signal synthesis; Wire;
Conference_Titel :
System Sciences, 1993, Proceeding of the Twenty-Sixth Hawaii International Conference on
Print_ISBN :
0-8186-3230-5
DOI :
10.1109/HICSS.1993.270626
