DocumentCode :
1612309
Title :
Hardware design of vector code correlation method for high-speed template matching
Author :
Yoshimura, Masaki ; Kawai, Hideki ; Iyota, Taketoshi ; Choi, Yongwoon
Author_Institution :
Dept. of Inf. Syst. Sci., Soka Univ., Tokyo
fYear :
2008
Firstpage :
2529
Lastpage :
2532
Abstract :
Template matching has been applied to the image processing of the fields such as security and robot vision to recognize a target from images. The method used in those fields requires the high-speed processing and robustness to illumination change or occlusion. To accommodate this, we employ a method, named the vector code correlation (VCC) that codes the gradient of intensity change, but the method on software is not enough in aspect of image processing time. Therefore, the purpose of this study is to achieve the template matching in real-time by designing hardware to implement the VCC method at high speed. The hardware design consists of five modules doing pipeline processing and is able to realize in relatively small scale. In the present paper, experimental results of 60 fps obtained with the designed hardware and its configuration are shown.
Keywords :
correlation methods; image coding; image matching; pipeline processing; VCC method; hardware design; high-speed processing; high-speed template matching; image processing time; intensity change gradient; pipeline processing; robot vision; vector code correlation; vector code correlation method; Correlation; Hardware; Image processing; Image recognition; Lighting; Pipeline processing; Robot vision systems; Robustness; Security; Target recognition; FPGA; Hardware design; Image processing; Template matching; Vector Code Correlation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Control, Automation and Systems, 2008. ICCAS 2008. International Conference on
Conference_Location :
Seoul
Print_ISBN :
978-89-950038-9-3
Electronic_ISBN :
978-89-93215-01-4
Type :
conf
DOI :
10.1109/ICCAS.2008.4694280
Filename :
4694280
Link To Document :
بازگشت