Self-timed neural model implementation: an example using CMAC

The author argues that a self-timed approach to digital neural hardware design is highly practical because it profits from the many benefits that self-timed methods bring to circuit design in general: scalability, robustness, average as opposed to worst-case performance, and freedom from global clock synchronization problems. The concepts discussed are demonstrated with a fully self-timed implementation of the cerebellar model articulation controller (CMAC) neural architecture suitable for VLSI. The author describes the CMAC model, presents a sample function for it to learn, documents its learning behaviour, and then shows how to implement a simplified CMAC.