Title :
HiBRIC-MEM, a memory controller for PowerPC based systems
Author :
Porrmann, M. ; Landmann, J. ; Marks, K.-M. ; Rückert, U.
Author_Institution :
Heinz Nixdorf Inst., Paderborn Univ., Germany
Abstract :
This paper describes the architecture and development of an innovative memory controller for the PowerPC family. HiBRIC-MEM (High Bandwidth Resource Interface Controller) provides control for up to two PowerPC processors. A look-ahead mechanism, called stream cache, is used to reduce the effective memory latency and a 12-bit error correction code is available for optimal system security. Initial silicon was produced in a 0.7 /spl mu/m, three metal layer Motorola technology and has a die size of 12.1/spl times/12.1 mm/sup 2/. HiBRIC-MEM is used, for example, in a commercially available parallel computer.
Keywords :
DRAM chips; cache storage; error correction codes; memory architecture; microcontrollers; multiprocessing systems; parallel architectures; parallel machines; DRAM; HiBRIC-MEM; High Bandwidth Resource Interface Controller; Motorola technology; PowerPC; die size; error correction code; look-ahead mechanism; memory controller; memory latency; optimal system security; parallel computer; silicon; stream cache; Bandwidth; Circuits; Clocks; Control systems; Delay; Electronic mail; Error correction codes; Logic testing; Master-slave; Random access memory;
Conference_Titel :
EUROMICRO 97. New Frontiers of Information Technology., Proceedings of the 23rd EUROMICRO Conference
Conference_Location :
Budapest, Hungary
Print_ISBN :
0-8186-8129-2
DOI :
10.1109/EURMIC.1997.617396
