Title :
From trace graphs to modular delay-insensitive circuits
Author :
Belhadj, Hichem ; Saucier, Gabrièle ; Yoeli, Michael
Author_Institution :
Inst. Nat. Polytech. Grenoble, France
Abstract :
The problem of synthesizing modular delay-insensitive circuits specified by a class of trace structures is considered. First, the notion of trace graphs is introduced for the purpose of facilitating the description of the relevant trace structures. Then, a theoretical framework within which the verification problem can be precisely formulated is established. It is shown how the dynamic behavior of a modular network may be derived from the specification of its component modules. The objective of this approach is to prove the correctness of the synthesis algorithm rather than verifying particular asynchronous circuits.
Keywords :
algorithm theory; asynchronous sequential logic; logic design; program verification; correctness; delay-insensitive circuits; dynamic behavior; modular delay-insensitive circuits; synthesis algorithm; trace graphs; Asynchronous circuits; Circuit synthesis; Clocks; Computer science; Delay; Integrated circuit interconnections; Network address translation; Network synthesis; Very large scale integration; Wires;
Conference_Titel :
System Sciences, 1993, Proceeding of the Twenty-Sixth Hawaii International Conference on
Print_ISBN :
0-8186-3230-5
DOI :
10.1109/HICSS.1993.270633
