Title :
A pipelined, expandable VLSI sorting engine implemented in CMOS technology
Author :
Ahn, Byoungchul ; Murray, John M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Abstract :
An improved implementation of the rebound sorter of T.C. Chen et al. (IEEE Proc. 4th Conf. of Very Large Databases, p.312-18, Sept. 1978) is described. The pipelining technique chosen is unique to this design. A single rebound sorting chip can sort eight 16-b records. By connecting these chips in a chain, it is possible to sort more than eight records. The VLSI version of the rebound sorter described in this paper is also simpler and smaller than many other sorters discussed in the literature. The Genesil silicon compiler, a commercial CAD tool, was used to implement the chip
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; microprocessor chips; pipeline processing; sorting; 16-b record sorting; CMOS technology; Genesil silicon compiler; Si compiler; chip connect; chip implementation; commercial CAD tool; expandable VLSI sorting engine; pipelining technique; rebound sorting chip; Business; CMOS technology; Engines; Hardware; Joining processes; Microarchitecture; Pipeline processing; Silicon compiler; Sorting; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100310
