• DocumentCode
    1612794
  • Title

    A self-timed wavefront array multiplier

  • Author

    Lau, C.H. ; Renshaw, D. ; Mavor, J.

  • Author_Institution
    Dept. of Electr. Eng., Edinburgh Univ., UK
  • fYear
    1989
  • Firstpage
    138
  • Abstract
    The application of self-timed logic to the design of a pipelined, parallel multiplier for two´s complement, fixed-point numbers is described. Self-timing is used so that temporal control is distributed over the elements that compose the system, allowing elements to interact locally to run at their optimum speed. The weighted summation of partial products is carried out using a carry-save array, with a last-stage carry-propagate adder to form the final product. With the provision for carry-completion detection, the carry-propagate addition can be completed in an average time that varies as log2 n for an n-bit adder
  • Keywords
    adders; multiplying circuits; parallel architectures; pipeline processing; carry-completion detection; carry-propagate addition; carry-save array; fixed-point numbers; last-stage carry-propagate adder; locally interacting elements; log2 n; n-bit adder; optimum speed; partial products; pipeline parallel multiplier design; self-timed logic; self-timed wavefront array multiplier; system elements; temporal control; weighted summation; Buildings; Clocks; Control systems; Distributed control; Fires; Logic design; Propagation delay; Signal generators; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1989., IEEE International Symposium on
  • Conference_Location
    Portland, OR
  • Type

    conf

  • DOI
    10.1109/ISCAS.1989.100311
  • Filename
    100311